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These 8-bit shift registers feature AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum setup time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.



  • Wide Operating Voltage Range of 2 V to 6 V
  •  Outputs Can Drive Up To 10 LSTTL Loads
  •  Low Power Consumption, 80-µA Max ICC
  •  Typical tpd = 20 ns ±4-mA Output Drive at 5 V
  •  Low Input Current of 1 µA Max
  •  AND-Gated (Enable/Disable) Serial Inputs
  •  Fully Buffered Clock and Serial Inputs
  •  Direct Clear


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